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KH300
Wideband, High-Speed Operational Amplifier
Features
I I I I I
General Description
The KH300 operational amplifier is a current feedback amplifier that provides a DC-85MHz -3dB bandwidth that is virtually independent of gain setting. Rise and fall times of 4ns and drive capability of 22Vpp and 100mA add to the KH300's impressive specifications. Using the KH300 is as easy as adding power supplies and a gain-setting resistor. Unlike conventional op amp designs in which optimum gain-bandwidth product occurs at a high gain, minimum settling time at a gain of -1, maximum slew rate at a gain of +1, et cetera, the KH300 offers consistent performance at gain settings from 1 to 40 inverting or non-inverting. As a result, designing with the KH300 is greatly simplified. And since no external compensation is necessary, "tweeks" on the production line have been eliminated, making the KH300 an efficient component for use in production situations. Flat gain and phase response from DC to 45MHz and superior rise and fall times make the KH300 an ideal amplifier for a broad range of pulse, analog, and digital applications. A 45MHz full power bandwidth (20Vpp into 100) and 3000V/sec slew rate eliminate the need for power buffers in many applications such as driving "flash" A to D converters or linedriving. For applications requiring lower power consumption, the KH300 can operate on supplies as low as 5V. Fast overload recovery (20ns) helps prevent loss of data in communications applications and flat phase response reduces distortion, even when data must be sent over extended lengths of line. The KH300A is packaged in a side-brazed 24-pin ceramic DIP and is specified at 25C.
-3dB bandwidth of 85MHz 3000V/sec slew rate 4ns rise and fall time 100mA output current Low distortion, linear phase
Applications
I I I I I I
Digital communications Baseband and video communications Instrument input/output amplifiers Fast A to D, D to A conversion Graphic CRT video drive amp Coaxial cable line driver
16
+VCC
V+
6
+
12
Vo
V-
8
1500
11
Rf
13
24
-VCC GND
KH300 Equivalent Circuit Diagram
Pin 11 provides access to a 1500 feedback resistor which can be connected to the output or left open if an external feedback resistor is desired. All undesignated pins are internally unconnected.
REV. 1A January 2004
DATA SHEET
KH300
KH300 Electrical Characteristics
magnitude of gain {|Vout/Vin|] PARAMETERS Frequency Domain Response -3dB bandwidth gain flatness phase shift deviation from linear phase reverse isolation distortion Time Domain Response rise and fall time CONDITIONS
(25C, VCC = 15V, RL = 100; unless noted) 4* TYP 105 45 0.25 0.5 1 2 60 MIN2 75 20 TYP 85 45 0.08 0.25 1.6 3 70 MAX2 40 TYP 70 45 0.25 1 2 5 70 UNITS MHz MHz dB dB deg/MHz deg dB
Vo < 4Vpp Vo = 20Vpp 100KHz to 20MHz 20MHz to 45MHz DC to 45MHz refer to graphs
0.3 0.6
5V output step 20V output step settling time to 0.8% 10V output step overshoot (input rise time 1ns) 5V output step slew rate overload recovery (200% od) < 50ns pulse width General Information input offset voltage (drift) input bias current (drift) CONDITIONS
3 7 20 5 3 20 MIN2
4 7 20 5 3 20 TYP 10(25) 10(20) 30(50) 48 100K/3 60 64 10, 100 24 MAX2 32 30 100 22 38
5 7 25 5 3 20
ns ns ns % V/s ns UNITS mV(V/C) V(nA/C) V(nA/C) V -dBc /pF dB dB V, mA mA
non-inverting inverting equivalent input noise1 integrated 0.1 to 100MHz, (Rs = 50, gain = 20) second/third harmonic distortion 20MHz, +10dBm input impedance non-inverting power supply rejection ratio input referred common mode rejection ratio input referred output drive voltage,current supply current
56
45
33
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. NOTES:
1) For Noise Figure, refer to Distortion and Noise section in text. 2) 100% tested at +25C, AV = +20, RL = 100, and VCC = 15V. * Refer to Low Gain Operation section.
Absolute Maximum Ratings
supply voltage (VCC) output current (Io) input voltage (Vimax) common mode input voltage power dissipation junction temperature (TJ) storage temperature still air thermal resistance (ca) 16V (5V min) 100mA (|VCC| - 2.5)/AV 1/2 |VCC| refer to graph 150C -55C to +150C +25C/W
2
REV. 1A January 2004
KH300
DATA SHEET
KH300 Performance Characteristics (25C, VCC = 15V, RL = 100; unless noted)
Non-Inverting Gain Inverting Gain
Relative Gain (1dB/div)
Av = 4
Relative Gain (1dB/div)
Av = 4
Av = 20
Av = 20 Av = 40
Av = 40
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Freguency (MHz) Broadband Inverting & Non-Inverting Gain
Av = 20
Freguency (MHz) Inverting & Non-Inverting Phase
Av = 20
Relative Gain (10dB/div)
0
Inverting
-180
-90
Non-inverting Inverting Non-inverting
-270
-180
-360
0
100 200 300 400 500 600 700 800 900 1GHz
0
10
20
30
40
50
60
70
80
90 100
Freguency (MHz) 2nd & 3rd Harmonic Distortion Intercept
90
Av = 20
Freguency (MHz) 2-Tone 3rd Order Intermod. Intercept
50
Av = 20
Intercept Point (+dBm)
Intercept Point (+dBm)
107 108
80 70 60 50 40 30 104
(I2) 2nd harmonic intercept exceeds 90dBm below 105Hz
45 40 35 30
(I3) 3rd harmonic intercept exceeds 64dBm below 105Hz
25 105 106 0 20 40 60 80 100
Freguency (Hz) Non-Inverting Small Signal Pulse Resp.
Av = 20
Freguency (MHz) Inverting Small Signal Pulse Response
Av = -20
Output Voltage (1V/div)
Time (5ns/div)
Output Voltage (1V/div)
Time (5ns/div)
REV. 1A January 2004
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DATA SHEET
KH300
KH300 Performance Characteristics (25C, VCC = 15V, RL = 100; unless noted)
Large Signal Pulse Response
0.4
Av = -20
Settling Time
10V step Av = 20
Output Voltage (2V/div)
0.2
Settling Error (%) Time (5ns/div)
0 -0.2 -0.4 -0.6 -0.8 0 200 400 600 800 1000
Time (ns) Relative Bandwidth vs. VCC
1.1
Av = 20
Power Dissipation Derating
2.5
Circuit Power Dissipation (W)
150C max TJ VCC = 15V
Relative Bandwidth
1.0
2.0
Case Ambient
0.9
1.5
0.8
1.0
0.7 4 6 8 10 12 14 16
0.5 -25 0 25 50 75 100
VCC (V) Equivalent Input Noise
100 100 80
Temperature (C) Common Mode Rejection Ratio
Voltage Noise (nV/Hz)
Current Noise (pA/Hz)
70
Inverting Current 11pA/Hz
CMRR (dB)
60 50 40 30 101 102 103 104 105 106 107
10
Voltage 2.9nV/Hz Non-inverting Current 2.3pA/Hz
10
1 102 103 104 105 106 107 108
1
Frequency (Hz) Power Supply Rejection Ratio
80 70
Frequency (Hz)
CMRR (dB)
60 50 40 30 101 102 103 104 105 106
Frequency (Hz)
4
REV. 1A January 2004
KH300
DATA SHEET
Layout Considerations To assure optimum performance the user should follow good layout practices which minimize the unwanted coupling of signals between nodes. During initial breadboarding of the circuit, use direct point to point wiring, keeping lead lengths to less than 0.25". The use of solid, unbroken ground plane is helpful. Avoid wire-wrap type pc boards and methods. Sockets with small, short pin receptacles may be used with minimal performance degradation although their use is not recommended.
+15
and 16. Larger tantalum capacitors should also be placed within one inch of these pins. To prevent signal distortion caused by reflections from impedance mismatches, use terminated microstrip or coaxial cable when the signal must traverse more than a few inches. Since the pc board forms such an important part of the circuit, much time can be saved if prototype boards of any high frequency sections are built and tested early in the design phase. Controlling Bandwidth and Passband Response As with any op amp, the ratio of the two feedback resistors Rf and Rg, determines the gain of the KH300. Unlike conventional op amps, however, the closed loop polezero response of the KH300 is affected very little by the value of Rg. Rg scales the magnitude of the gain, but does not change the value of the feedback. Rf does influence the feedback and so the KH300 has been internally compensated for optimum performance with Rf = 1500, but any value of Rf > 500 may be used with a single capacitor placed between pins 8 and 12 for compensation. See table 1. As Rf decreases, Cc must increase to maintain flat gain. Large values of Rf and Cc can be used together or separately to reduce the bandwidth. This may be desirable for reducing the noise bandwidth in applications not requiring the full frequency response available. Table 1: Bandwidth vs. Rf and Cc (Av = +20)
0.01F Vin Ri 50 Rg
22F 16 6
8
+ 11 KH300 24
13
12
Ro 50
1/2 Vo RL 50
-15 22F 0.01F Av = 1 + Rf Rg
Rf = 1500 (internal)
Figure 1: Recommended Non-inverting Gain Circuit
+15
Rf (K)
0.01F 51 22F 6 16
Cc (pF) 0 0 0 0 0.3 1.1 1.9
f0.3dB (MHz) 2 3 8 45 90 95 110
f-3.0dB (MHz) 5 12 40 85 115 130 135
Vin Ri 50
Rg
8
+ 11 KH300 24
13
12
Ro 50
1/2 Vo RL 50
10.0 5.0 2.0 1.5 1.0 0.75 0.50
-15 22F 0.01F For Zin = 50 Select: Rg||Ri = 50 Rf -Av = Rg Rf = 1500 (internal)
Figure 2: Recommended Inverting Gain Circuit During pc board layout keep all traces short and direct. Rf and Rg should be as close as possible to pin 8 to minimize capacitance at that point. For the same reason, remove ground plane from the vicinity of pins 8 and 6. In other areas, use as much ground plane as possible on one side of the pc board. It is especially important to provide a ground return path for current from the load resistor to the power supply bypass capacitors. Ceramic capacitors of 0.01 to 0.1F should be close to pins 13
Low Gain Operation The small amount of stray capacitance present at the inverting input can cause peaking which increases with decreasing gain. The gain setting resistor Rg is effectively in parallel with this capacitance and so a frequency domain pole results. With small Rg (Gain > 8), this pole is at a high frequency and it affects the closed loop gain of the KH300 only slightly. At lower values of gain, this pole becomes significant. For example, at a gain of +2, the gain may peak as much as 3dB at 75MHz, and have a bandwidth exceeding 150MHz. The same behavior does not exist for low inverting gains, however, since the inverting input is a virtual ground which maintains a constant voltage across the stray capacitance. Even at inverting gains << 1, the frequency response remains unchanged.
REV. 1A January 2004
5
DATA SHEET
KH300
To avoid the peaking at low non-inverting gains, place a resistor Rp in series with the input signal path just ahead of pin 6, the non-inverting input. This forms a low pass filter with the capacitance at pin 6 which can be made to cancel the peaking due to the capacitance at pin 8, the inverting input. At a gain of +2, for example, choosing Rp such that the source impedance in parallel with Ri (see Figure 1), plus Rp equals 175 will flatten the frequency response. For larger gains, Rp will decrease. Settling Time, Offset, and Drift After an output transition has occurred, the output settles very rapidly to final value and no change occurs for several microseconds. Thereafter, thermal gradients inside the KH300 will cause the output to begin to drift. When this can not be tolerated, or when the initial offset voltage and drift is unacceptable, the use of a composite amplifier is advised. This technique reduces the offset and drift to that of a monolithic, low frequency op amp, such as an LF356A. The composite amplifier technique is fully described in the KH103 data sheet. A simple offset adjustment can be implemented by connecting the wiper of a potentiometer, whose end terminals connect to 15V, through a 20K resistor to pin 8 of the KH300. Overload Protection To avoid damage to the KH300, care must be taken to insure that the input voltage does not exceed (|VCC| 2.5)/AV. High speed, low capacitance diodes should be used to limit the maximum input voltage to safe levels if a potential for overload exists. If in the non-inverting configuration the resistor Ri, which sets the input impedance, is large, the bias current at pin 6, which is typically a few pA but which may be as large as 18A, can create a large enough input voltage to exceed the overload condition. It is therefore recommended that Ri < [(|VCC| -2.5)/ AV]/(18A).
Distortion and Noise The graphs of intercept point versus frequency on the preceding page make it easy to predict the distortion at any frequency, given the output voltage of the KH300. First, convert the output voltage (Vo) to Vrms = (Vpp/22) and then to P = (10log10(20Vrms2)) to get output power in dBm. At the frequency of interest, its 2nd harmonic will be S2 = (I2 - P) dB below the level of P. Its third harmonic will be S3 = 2 (l3 = P) dB below P as will the two tone third order intermodulation products. These approximations are useful for P < -1dB compression levels. Approximate noise figure can be determined for the KH300 using the Equivalent Input Noise graph on the preceding page. The following equation can be used to determine noise figure (F) in dB: vn2 + F = 10 log 1 + in 2R f 2 A v2
4 kTR s f
Where vn is the rms noise voltage and in is the rms noise current. Beyond the breakpoint at the curves (i.e., where they are flat), broadband noise figure equals spot noise figure, so f should equal one (1) and vn and in should be read directly off of the graph. Below the breakpoint, the noise must be integrated and f set to the appropriate bandwidth.
6
REV. 1A January 2004
DATA SHEET
KH300
KH300 Package Dimensions 2
Pin #1 Index Q L E e D1 D A1 E1 b1 A C
b
Symbol
A-Metal Lid A-Ceramic Lid A1-Metal Lid A1-Ceramic Lid b b1 c D D1 E E1 e L Q
Inches
Minimun 0.180 0.195 0.145 0.160 0.014 Maximum 0.240 0.255 0.175 0.190 0.026
Milimeters
Minimum 4.57 4.95 3.68 4.06 0.36 Maximum 6.10 6.48 4.45 4.83 0.66
0.050 BSC 0.008 1.275 1.095 0.785 0.790 0.018 1.310 1.105 0.815 0.810
1.27 BSC 0.20 33.39 27.81 19.94 20.07 0.46 33.27 28.07 20.70 20.57
0.100 BSC 0.165 BSC 0.015 0.075
2.54 BSC 4.19 BSC 0.38 1.91
NOTES: Seal: seam weld (AM, AK), epoxy (AI) Lead finish: gold finish
Package composition: Package: ceramic Lid: kovar/nickel (AM, AK), ceramic (AI) Leadframe: alloy 42 Die attach: epoxy
Life Support Policy Cadeka's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Cadeka Microcircuits, Inc. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Cadeka does not assume any responsibility for use of any circuitry described, and Cadeka reserves the right at any time without notice to change said circuitry and specifications.
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(c) 2004 Cadeka Microcircuits, LLC

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